The present invention concerns a gate overlapped lightly doped drain (GOLDD) process for use in producing high reliability submicron metal oxide semiconductor field effect transistors (MOSFETs).
The use of GOLDD processes for high speed reliable submicron MOSFETs has been investigated. For example, in one process, referred to as total overlap with polysilicon spacer (TOPS), three deposits of polysilicon are use to form a gate region of a transistor which overlaps the source and drain region of the transistor. See J. E. Moon, et al., A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS), IEEE Electronic Device Letters, May 1990, pp. 221-223. See also T. Y Huang: A novel SubMicron LDD Transistor with Inverse-T Gate Structure, IEDM, 1986, pp, 742-745, and R. Izawa, et. al., The Impact of Gate-Drain Overlapped LDD(GOLD) For Deep SubMicron VLSIs, IEDM 1987, pp. 38-41.
The presence of an overlapping gate in submicron processing of MOSFETs has several advantages. For example, devices which use overlapping gates show improvements in performance and reliability. Further, such devices have shown a smaller sensitivity to n.sup.- dose variations. However, existing GOLDD processes are complex and not suitable for use in a volume production environment. For example, the three polysilicon depositions required for the TOPS process makes the process impractical for use in manufacturing VLSI circuits. It is desirable, therefore, to develop methods to produce MOSFETs using GOLDD processes which are also suitable for use in a manufacturing environment.